Hi,
I was looking through the code for the eth_wishbone module and I saw this:

always @ (posedge WB_CLK_I)
begin
WB_ACK_O end


I am curious, is there any reason why when a read is being performed
the ack is generated on the transition of WbEn & WbEn_q while a write
is acknowledged when both WbEn & WbEn_q are set?

Is it possible to generate the ack for both read and write on the
transition of WbEn & WbEn_q? or is there a logical reason not to
operate in this manner?

WB_ACK_O
Cheers,
Eoin Creedon